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TRF3702
www.ti.com
SLWS149A – SEPTEMBER 2004 – REVISED AUGUST 2006
APPLICATION INFORMATION (continued)
DRIVING THE LOCAL OSCILLATOR INPUT
The LO pin is internally terminated to 50 ? , thus enabling easy interface to the LO source without the need for
external impedance matching. The power level of the LO signal should be in the range of –6 dBm to 6 dBm. For
characterization purposes, a power level of 0 dBm was chosen. An ideal way of driving the LO input of the
TRF3702 is by using the TRF3750, an ultralow-phase-noise integer-N PLL from Texas Instruments. Combining
the TRF3750 with an external VCO can complete the loop and provide a flexible, convenient, and cost-effective
solution for the local oscillator of the transmitter. Figure 68 shows a typical application for the LO driver network
that incorporates the TRF3750 integer-N PLL synthesizer into the design. Depending on the VCO output and the
amount of signal loss, an optional gain stage may be added to the output of the VCO before it is applied to the
TRF3702 LO input.
DVDD
+
10 pF
AVDD
VCP
VVCO
10 m F
0.1 m F
+
10 pF
10 pF
0.1 m F
+
10 m F
10 pF
+
To TRF3702
LO Input
10 m F
0.1 m F
0.1 m F
10 m F
100 pF
SUPPLY
10
CE
VCP
16
16.5 W
1 nF
GND
TCXO
(10-MHz Reference)
8
REFIN CPOUT
TRF3750
2
1 nF
20 k W
10 nF
V TUNE
82 pF
GND
VCO
OUT
100 pF
GND
16.5 W
16.5 W
DECOUPLING NOT SHOWN
RSET
1
RSET
3.9 k W
4.7 k W
CLK
11
CLK
RFINA
6
DATA
LE
12
13
DATA
LE
MUXOUT
RFINB
14 LOCK DETECT
5
100 pF
49.9 W
3 4 9
100 pF
S0009-02
Figure 68. Typical Application Circuit for Generating the LO Signal for the TRF3702 Modulator
PCB LAYOUT CONSIDERATIONS
The TRF3702 is a high-performance RF device; hence, care should be taken in the layout of the PCB in order to
ensure optimum performance. Proper decoupling with low-ESR ceramic chip capacitors is needed for the VCC
supplies (pins 6 and 10). Typical values used are in the order of 1 pF parallel to 0.1 μ F, with the lower-valued
capacitors placed closer to the device pins. In addition, a larger tank capacitor in the order of 10 μ F should be
placed on the supply line as layout permits. At least a 4-layer board is recommended for the PCB. If possible, a
solid ground plane and a ground pour is also recommended, as is a power plane for the supplies. Because the
balance of the four I, Q inputs to the modulator can be critical to device performance, care should be taken to
ensure that the trace runs for all four inputs are equal in length. In the case of single-ended drive of the I, Q
inputs, the two unused pins IREF and QREF are fed with the VCM dc voltage only, and should be decoupled
with a 0.1- μ F capacitor (or smaller). The LO input trace should be minimized in length and have controlled
impedance of 50 ? . No external matching components are needed because there is an internal 50- ?
termination. The RFOUT pin should also have a relatively small trace to minimize parasitics and coupling, and
should also be controlled to 50 ? . An impedance-matching network can be used to optimize power transfer, but
is not critical. All the results shown in the data sheet were taken with no impedance matching network used
(RFOUT directly driving an external 50- ? load).
The exposed thermal and ground pad on the bottom of the TRF3702 should be soldered to ground to ensure
optimum electrical and thermal performance. The landing pattern on the PCB should include a solid pad and 4
thermal vias. These vias typically have 1,2-mm pitch and 0,3-mm diameter. The vias can be arranged in a 2 × 2
array. The thermal pad on the PCB should be at least 1,65 × 1,65 mm. A suggested layout is shown in Figure 69 .
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